The present invention relates to improved electronic circuits for the transmission of data between different clock domains. More particularly, the present invention relates to electronic circuits useful for the conformational representation of signals communicated between parts of circuits having different frequency clocks.
Many electronic circuits and domains within circuits operate at rates which are determined by clock cycles generated at a particular domain clock frequency and transmitted to them. The term clock domain is used hereinunder to mean those parts of an electronic circuit that operate at the rate of a particular clock. These clock frequencies often vary among said clocks domains, varying accordingly the operating frequencies of the circuits in their domains. It is often necessary to generate a digital representation of the duration of a signal, expressed in terms of the number of clock cycles of its domain of origin, represented by signals of that domain frequency, and to transmit this digital representation to a destination clock domain, while converting the digital representation, generated by the origin domain clock, to that of the destination domain clock frequency.
In the past, when a signal needed to be transmitted from a fast clock domain to a slow clock domain, the signal would first need to be written by a processor from the fast clock domain to random access memory across a bus. Then a processor in the slow clock domain could read the signal across the bus from the random access memory at its own slow clock speed. However, this architecture and process requires a large number of read/write operations which directly affects the overall efficiency and performance of a system so designed.
The conversion of the transmitted digital representation of the number of clock cycles forming a signal from one clock domain frequency into another clock domain frequency, while retaining the number of cycles, is called hereinunder xe2x80x9cconformationxe2x80x9d.
As alluded to above, conformation poses problems, and particularly in the two following cases:
transmission of signal representation by slow clock signals (hereinbelow LF), i.e. long clock cycles, to a fast clock signal, short clock cycle domain (hereinbelow HF). In this case, some or all of the LF clock cycles may be sampled more than once by an HF domain device, leading to erroneous interpretation of the signal by the HF domain; and
transmission of signal duration representation by HF clock cycles to an LF domain. In this case, sampling of HF clock cycles by an LF clocked device may lead to erroneous interpretation of the signal as some of the short HF cycles will not be sampled by the LF device at all or an HF signal that is not a full integer multiple of LF cycles in length will be assigned an incorrect length by the LF device.
It is the purpose of the present invention to offer efficient circuits that overcome the aforementioned problems.
This is accomplished by the following two kinds of methods:
[1] For transmitting a data signal from a fast clock domain directly to a slow clock domain, a circuit, which bridges the two domains, detects the presence or absence of signal at every clock cycle in the fast domain, presence or absence being assigned a value, e.g. high vs. low (or 1 vs. 0) for each clock cycle. A plurality of the clock signal detection values is transmitted in parallel to a counter in the slow clock domain wherein each clock signal detection value is recorded as being a high or a low, and wherein the total number of detected high values or detected low values is output as a binary number by counter, thus informing the slow clock domain of the true number of clock cycles of which the signal is comprised; and
[2] For transmitting a data signal from a slow clock domain directly to a fast clock domain, a circuit which bridges the two domains comprises, in the slow clock domain, an edge detector for detecting the rising edge or falling edge of an incoming signal. When the edge detector detects a signal""s leading edge, it causes the reversal of the state of flip-flops in both the slow domain and the fast domain, thereby signifying advent of a signal. Reversal of the flip-flops in the slow domain for each clock cycle when a signal is passing, is detected in the fast domain and understood by the fast domain as being caused by a new slow clock cycle, thereby sensitizing the fast clock domain to the beginning and ending of slow clock cycles which it would otherwise lump together as being a single clock cycle.